This invention relates generally to the use and structure of removable nonvolatile memory devices, particularly those having standardized interfaces for connecting with other electronic systems.
Electronic circuit cards, including non-volatile memory cards, have been commercially implemented according to a number of well-known standards. Memory cards are used with personal computers, cellular telephones, personal digital assistants (PDAs), digital still cameras, digital movie cameras, portable audio players and other host electronic devices for the storage of large amounts of data. Such cards usually contain a re-programmable non-volatile semiconductor memory cell array along with a controller that controls operation of the memory cell array and interfaces with a host to which the card is connected. Several of the same type of card may be interchanged in a host card slot designed to accept that type of card. However, the development of the many electronic card standards has created different types of cards that are incompatible with each other in various degrees. A card made according to one standard is usually not useable with a host designed to operate with a card of another standard. Memory card standards include PC Card, CompactFlash™ card (CF™ card), SmartMedia™ card, MultiMediaCard (MMC™), Secure Digital (SD) card, a miniSD™ card, Subscriber Identity Module (SIM), Memory Stick™, Memory Stick Duo card and TransFlash™ memory module standards. Small, hand-held re-programmable non-volatile memories have also been made to interface with a computer or other type of host through a Universal Serial Bus (USB) connector. There are several USB flash drive products commercially available from SanDisk Corporation under its trademark “Cruzer®.” USB flash drives are typically larger and shaped differently than the memory cards described above.
Two general memory cell array architectures have found commercial application, NOR and NAND. In a typical NOR array, memory cells are connected between adjacent bit line source and drain diffusions that extend in a column direction with control gates connected to word lines extending along rows of cells. A memory cell includes at least one storage element positioned over at least a portion of the cell channel region between the source and drain. A programmed level of charge on the storage elements thus controls an operating characteristic of the cells, which can then be read by applying appropriate voltages to the addressed memory cells. Examples of such cells, their uses in memory systems and methods of manufacturing them are given in U.S. Pat. Nos. 5,070,032; 5,095,344; 5,313,421; 5,315,541; 5,343,063; 5,661,053 and 6,222,762.
The NAND array utilizes series strings of more than two memory cells, such as 16 or 32, connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells within a large number of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell. Examples of NAND architecture arrays and their operation as part of a memory system are found in U.S. Pat. Nos. 5,570,315; 5,774,397; 6,046,935; 6,456,528 and 6,522,580.
The charge storage elements of current flash EEPROM arrays, as discussed in the foregoing referenced patents, are most commonly electrically conductive floating gates, typically formed from conductively doped polysilicon material. An alternate type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of the conductive floating gate to store charge in a non-volatile manner. In one example, a triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (ONO) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region, and erased by injecting hot holes into the nitride. Several specific cell structures and arrays employing dielectric storage elements are described in U.S. Pat. No. 6,925,007.
Individual flash EEPROM cells store an amount of charge in a charge storage element or unit that is representative of one or more bits of data. The charge level of a storage element controls the threshold voltage (commonly referenced as VT) of its memory cell, which is used as a basis of reading the storage state of the cell. A threshold voltage window is commonly divided into a number of ranges, one for each of the two or more storage states of the memory cell. These ranges are separated by guardbands that include a nominal sensing level that allows determining the storage states of the individual cells. These storage levels do shift as a result of charge disturbing programming, reading or erasing operations performed in neighboring or other related memory cells, pages or blocks. Error correcting codes (ECCs) are therefore typically calculated by the controller and stored along with the host data being programmed and used during reading to verify the data and perform some level of data correction if necessary.
Memory cells of a typical flash EEPROM array are divided into discrete blocks of cells that are erased together. That is, the block (erase block) is the erase unit, a minimum number of cells that are simultaneously erasable. Each erase block typically stores one or more pages of data, the page being the minimum unit of programming and reading, although more than one page may be programmed or read in parallel in different sub-arrays or planes. Each page typically stores one or more sectors of data, the size of the sector being defined by the host system. An example sector includes 512 bytes of host data, following a standard established with magnetic disk drives, plus some number of bytes of overhead information about the host data and/or the erase block in which they are stored. Such memories are typically configured with 16, 32 or more pages within each erase block, and each page stores one or more sectors of host data. Host data may include user data from an application running on the host and data that the host generates in managing the memory such as FAT (file allocation table) and directory data.
A memory array is generally formed on a die (“memory die” or “chip”) that may also have peripheral circuits that are connected to the memory array. Examples of peripheral circuits include row and column control circuits, registers, state machines, charge pumps and other circuits associated with reading, writing and erasing data in a memory array.
A memory controller may have several components including a central processing unit (CPU), a buffer cache (buffer RAM) and a CPU RAM. Both buffer RAM and CPU RAM may be SRAM memories. These components may be on the same die or on separate dies. The CPU is a microprocessor that runs software (firmware) to carry out operations including transferring data to and from the memory array. In one example shown in U.S. Pat. No. 5,297,148, which is incorporated herein in its entirety, a buffer cache may be used as a write cache to reduce wear on a flash EEPROM that is used as non-volatile memory. In one arrangement, a memory controller is formed as an Application Specific Integrated Circuit (ASIC) so that a single integrated circuit (controller die or chip) performs all memory controller functions.
Some memory cards may be used with different hosts that do not always use the same standards. For example, some hosts may provide power to a memory card at 3.3 volts, while others may provide power at 1.8 volts. Cards that operate with host power supplies at two different voltage levels may be considered to be dual voltage memory cards.
FIG. 1 shows a dual voltage memory card 100 of the prior art having a dual voltage controller die 102 connected to a dual voltage memory die 104. Both controller die 102 and memory die 104 receive their power from a host through a common contact 106 at a voltage VDD supplied by the host. Internal circuits in both controller die 102 and memory die 104 allow each die to operate whether the host provides VDD at 3.3 volts or 1.8 volts. Also shown in FIG. 1 is a common ground contact 108 providing a ground voltage VSS to both the controller die and the memory die. In addition, contacts 110a-d are provided for exchange of data, command and status information.